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Step-by-Step Functional Verification with SystemVerilog and OVM



Step-by-Step Functional Verification with SystemVerilog and OVM

Author: Sasan Iman

Publisher: Hansen Brown Publishing

Genres:

Publish Date: Publish Date

ISBN-10: 0981656218

Pages: Pages

File Type: PDF

Language: English

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Book Preface

By now, the metaphor of “the perfect storm” is in danger of becoming a cliche to describe the forces causing rapid evolution in some aspect of the electronics industry. Nevertheless, the term is entirely applicable to the current evolution arguably even a revolution-in functional verification for chip designs. Three converging forces are at work today: complexity, language, and methodology.

The challenges posed in the verification oftoday’s large, complex chips is well known. Far too many chips do not ship on first silicon due to functional bugs that should have been caught before tapeout. Hand-written simulation tests are being almost entirely replaced by constrained-random verification environments using functional coverage metrics to determine when to tape out. Specification of assertions, constraints, and coverage points has become an essential part of the development process.

The System Verilog language has been a major driver in the adoption of these advanced verification techniques. System Verilog provides constructs for assertions, constraints, and coverage along with powerful object-oriented capabilities that foster reusable testbenches and verification components. The broad vendor support and wide industry adoption of System Veri log have directly led to mainstream use of constrained-random, coverage-driven verification environments.

However, a language alone cannot guarantee successful verification. System Verilog is a huge language with many ways to accomplish similar tasks, and it doesn’t directly address such essential areas as verification planning, common testbench building blocks, and communication between verification components. Such topics require a comprehensive verification methodology to tie together the advanced techniques and the features of the language in a systematic approach.

Fortunately, the Open Verification Methodology (OVM) recently arrived to address this critical need. Developed by Cadence Design Systems and Mentor Graphics, the OVM is completely open (freely downloadable from ovmworld.org) and guaranteed to run on the simulation products from both companies. The OVM leverages many years of verification experience from many of the world’s experts. It was greeted with enormous enthusiasm by the industry and is used today on countless chip projects.

Thus, the timing of this book could not be better. It provides thorough coverage of all three forces at work. The complexity challenge is addressed by timely advice on verification planning and coherent descriptions of advanced verification techniques. Many aspects of the System Verilog language, including its assertion and testbench constructs, are covered in detail. Finally, this book embraces the OVM as the guide for verification success, providing a real-world example deploying this methodology.

Functional verification has never been easy, but it has become an overwhelming problem for many chip development teams. This book should be a great comfort for both design and verification engineers. Perhaps, like The Hitchhiker s Guide to the Galaxy, it should have “DON’T PANIC!” on its cover. So grab a beverage of your choice and curl up in a comfortable chair to learn how to get started on your toughest verification problems.


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